This application is related to co-pending application entitled xe2x80x9cCyclic thermal Anneal For Dislocation Reduction,xe2x80x9d filed on even date herewith and incorporated by reference in its entirety.
This invention relates to metal-oxide-semiconductor (MOS) structures formed on a semiconductor layer, such as germanium, and more particularly relates to a method of forming an insulating layer on a germanium layer.
Integration of germanium (Ge)-based electronic devices such as near-infrared photodetectors and near-infrared phototransistors on a silicon (Si) substrate is recognized as an important technological challenge for enabling improvements in the functionality of Si integrated circuits. Two particular and related difficulties in the integration of Ge with a silicon device fabrication sequence are posed by the high chemical activity of Ge in conventional Si wafer cleaning chemistry and the inability to oxidize Ge directly to form a robust, high-quality oxide layer.
Conventionally, electronic devices on a silicon substrate are protected during various cleaning processes by a layer of silicon dioxide (SiO2) formed by, e.g., chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). Ge is very highly reactive with most conventional Si cleaning chemicals and therefore any Ge layers produced on a Si substrate must be well-shielded from cleaning steps carried out in a Si fabrication sequence. Although there are well-developed techniques for depositing a layer of SiO2 by CVD or PECVD on a Ge layer, such layers cannot, in practice, be exploited as both a shield against cleaning processes and as the oxide layer in a MOS structure formed on a Ge layer. This is due to the characteristically poor electrically qualities of CVD and PECVD oxide layers.
Specifically, SiO2 deposited by CVD or PECVD typically contains hydrogen and/or chlorine, resulting in a relatively low dielectric strength. Furthermore, such films are generally characterized by a high density of trapped electrical charges. These well-known limitations of CVD and PECVD SiO2 films have led to the universal use of thermally-grown, rather than deposited, SiO2 films as the gate oxide in silicon MOS structures and devices. It is not possible, however, to thermally oxidize germanium in the manner of silicon to produce a useful dielectric layer. This process obstacle has been addressed by various proposed processes for depositing a CVD or PECVD SiO2 film on Ge in a manner that minimizes the deleterious characteristics of the film.
It has been recognized that whatever the quality of a SiO2 film itself, the SiO2film/Ge interface is generally characterized by a high density of electrical interface states. Such can result in a high surface leakage current when a P-N junction is terminated at the interface. The electrical qualities of the interface are generally so poor as to not be suitable for fabrication of MOS devices. It has been proposed to alleviate this condition and to produce a relatively higher quality SiO2 layer on Ge by inserting a layer of Si of low thickness, e.g., less than about 2 nm in thickness, between a PECVD SiO2 film and the Ge layer. Although the use of a Si interlayer has been shown to improve interface characteristics, it does not generally improve the quality of the PECVD SiO2 film.
Thus, the quality of SiO2 films produced by current, conventional CVD and PECVD processes are generally far below the quality required for gate oxide films in Si CMOS technology; only gate oxide films produced by thermal oxidation are commercially viable. As a result, in a conventional fabrication sequence employing both Si and Ge, a CVD or PECVD oxide deposition process is required for the Ge regions, and a thermal oxide growth process is required for the Si regions. This duplication in oxide formation processes results in lower throughput and higher cost, and reduces the commercial viability of the Si-Ge fabrication.
The invention provides processes for producing a high-quality silicon dioxide layer on a germanium layer. In one example process, a layer of silicon is deposited on the germanium layer, and then the silicon layer is exposed to dry oxygen gas at a temperature that is sufficient to induce oxidation of the silicon layer substantially only by thermal energy. In a further example process, the silicon layer is exposed to water vapor at a temperature that is sufficient to induce oxidation of the silicon layer substantially only by thermal energy.
For many applications, it can be preferred that the exposure to dry oxygen gas or to water vapor be carried out in an oxidation chamber at a chamber pressure that is no less than ambient pressure. In one example, the chamber pressure is above about 2 atm. The temperature at which the silicon layer is exposed to the dry oxygen gas is preferably above about 500xc2x0 C., more preferably above about 600xc2x0 C., even more preferably above about 700xc2x0 C., and most preferably above about 800xc2x0 C.
The exposure to dry oxygen gas can be carried out for a duration of time selected to oxidize substantially the entire silicon layer or alternatively, for a duration of time selected to oxidize a portion of the silicon layer. The silicon layer can be of a thickness of, e.g., between about 5 angstrom and about 500 nanometer. The un-oxidized portion of the silicon layer preferably is at least about one silicon monolayer thick.
In processes provided by the invention, a first step can be carried out to grow the germanium layer on a silicon substrate. Desorption of native oxide of the germanium layer can be carried out prior to the silicon layer deposition. The silicon layer deposition can be carried out in situ with and following the germanium growth. The germanium layer and the silicon layer can each be deposited in an ultra high vacuum chamber by chemical vapor deposition.
After the oxidation process, the oxidized silicon layer can be annealed in accordance with the invention. An electrically conductive element can be formed on the oxidized silicon layer; for example, a metal layer can be deposited on the oxidized silicon layer. This enables the formation of MOS structures and devices for a wide range of applications in a manner that is commercially viable.
Other features and advantages of the invention will be apparent from the following description and the accompanying drawings, and from the claims.